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ASIC/ VLSI / EDA
Physical Design Manager
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Minimum 6 years of ASIC physical design experience.
Leadership and Mentoring skills a must.
Management experience an asset.
Strong Back ground of ASIC Physical Design: Floor planning, P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
Scripting Language with PERL, TCL, AWK, shell scripting a very big asset.
Familiar with Physical Verification is also desirable.
| | Experience | : | 8 - 15 yrs
| | Job Description | : | Key Responsibilities
The Physical Design Manager will be responsible for the planning and execution of all physical design activities for a given ASIC products. She/he will be responsible to manage a group of 6 to 12 engineers on Physical Design (place and route) duties both on block, as well as global top-level, which includes: top-level floor planning, placement, scan-reordering, clock tree synthesis, in place optimization, routing, timing analysis/closure and ECO tasks (timing, functional, noise based ECOs), design rule checks (DRC), and Logical vs. Schematic (LVS) checks.
The candidate will be responsible for:
- Resource management, hiring and training.
- Provide technical direction, mentoring, skill development
- Forward thinker to improve process and innovation
- Interface with other ASIC Managers/Directors to define schedules, resource requirements,
- Provide leadership and direction in crisis
- Interface with front-end ASIC teams to resolve issues and problems
- Responsible for execution of program. Multiple projects on the go
In addition, strong communication skills and an ability to work in large groups are essential to being successful. Some insight to multi-site project development will be an asset.
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Physical design/Backend Design
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Leadership and Mentoring skills a must.
Strong Back ground of ASIC Physical Design : Floor planning , P&R extraction, IR Drop Analysis, timing and Signal Integrity closure.
Hands on experience and detailed knowledge in Cadence or Synopsys or Magma ASIC Physical Design Tools
Scripting Language with PERL ,TCL,AWK, shell scripting a very big asset.
Familiar with Physical Verification is also desirable.
| | Experience | : | 3 - 10 yrs
| | Job Description | : | Would be responsible for physical design and verification of large SoCs.
Should have excellent hands-on experience pertaining to Floorplanning and Power Grid design, Clocktree, Timing and congestion driven Routing and Chip Finishing and physical verification for large SoCs.
Should have excellent knowledge of DSM effect analysis ranging from IR Drop, EM, and Cross talk analysis.
Knowledge of layout enhancements for DFM compliance desired. Working experience with SoC Encounter, Calibre, Virtuoso, Primetime, VoltageStorm, Celtic is a pre-requisite for the job. Experience in 65nm technology is a plus.
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Analog Design Engineer / Leads
| | Skills | : | Responsible for architecture definition and design of analog blocks like ADC/DAC, Sigma-Delta, PLL's, High Speed PHY's, High voltage designs, RF.
Knowledge of CMOS analog circuit design concepts, understanding of devices and process technology to be able to do complex circuit design, proficiency in use of EDA tools for schematic capture, circuit simulation (SPICE), layout and post-layout verification is essential. Good understanding of system requirements and specifications of the block is required. Knowledge of digital design flow (synthesis/simulation) and Verilog behavioral modeling is useful.
| | Experience | : | 2 - 10 yrs
| | Job Description | : | Responsible for architecture definition and design of analog blocks like ADC/DAC, Sigma-Delta, PLL's, High Speed PHY's, High voltage designs, RF.
Knowledge of CMOS analog circuit design concepts, understanding of devices and process technology to be able to do complex circuit design, proficiency in use of EDA tools for schematic capture, circuit simulation (SPICE), layout and post-layout verification is essential. Good understanding of system requirements and specifications of the block is required. Knowledge of digital design flow (synthesis/simulation) and Verilog behavioral modeling is useful
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I/O Design
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Primary and Secondary Responsibilities: IO Schematic Design in 45nm and below. Layout Knowledge (Wish list)
Complex Tasks: Should be willing to take initiative and multi task.
Management/Organizational Skills: Good Communication and Leadership Skills required for handling any future responsibilities
Team and People Skills: Good Leadership skills required. Should not be very introvert (Wish list).
Projects and Deliverables: Low Leakage IO Design, High Speed IO design, PTV Compensated IO design.
Unique selling features of this position, team, or project:
Potential Projects for the candidate: Low Leakage IO Design, High Speed IO design, Process Compensated IO design.
Team Selling Features: Team Owns the Worldwide Semiconductor IO design leadership. All kinds of Interface standards are designed here. Team is already working on 45nm and below technologies and is actively involved in defining the new Interface Standards.
| | Experience | : | 2 - 12 yrs
| | Job Description | : | Primary and Secondary Responsibilities: IO Schematic Design in 45nm and below. Layout Knowledge (Wish list)
Complex Tasks: Should be willing to take initiative and multi task.
Management/Organizational Skills: Good Communication and Leadership Skills required for handling any future responsibilities
Team and People Skills: Good Leadership skills required. Should not be very introvert (Wish list).
Projects and Deliverables: Low Leakage IO Design, High Speed IO design, PTV Compensated IO design.
Unique selling features of this position, team, or project:
Potential Projects for the candidate: Low Leakage IO Design, High Speed IO design, Process Compensated IO design.
Team Selling Features: Team Owns the Worldwide Semiconductor IO design leadership. All kinds of Interface standards are designed here. Team is already working on 45nm and below technologies and is actively involved in defining the new Interface Standards.
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FPGA Design
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Knowledge with digital and analog communication methods including RS232/485, T1/E1, Ethernet, GbE, 10GbE, DS3, SONET/SDH, ATM, ESCON, FICON, Fibre Channel, and other storage area network protocols.
5. Strong hardware analysis, design, FPGA/CPLD coding, testing, and documentation skills.
| | Experience | : | 5 - 12 yrs
| | Job Description | : | Motorola based microprocessor designs
2. Board level designs including digital and analog subsections using schematic entry tools
3. Develop CPLD and FPGA logic architecture, code, simulation, and verification
4. Hands on bench testing of new designs for compliance to design specifications
5. Complete documentation throughout design and development cycle from theory of operation to test specifications
6. Responsible for communication and coordination with Software, Hardware, Integration and Test, System Engineering, Validation, and Manufacturing teams throughout the design and development cycle
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ASIC Design Engineers /Leads
| | Company | : | A Leading Semiconductor Company
| | Skills | : | 4 to 10 years of complex high speed ASIC Design experience.
Exposure to Digital systems and VLSI design, Computer Architecture, Computer Arithmetic, C++ programming languages, CMOS transistors and circuits is required.
Previous design experiences in a project leadership role a plus.
Previous experience mentoring junior engineers a plus
Good communications skills and ability and desire to work as a team player are a must.
BSEE, MSEE or PhD and CGPA of 8.0 out of 10.0 or higher is required.
| | Experience | : | 4 - 10 yrs
| | Job Description | : | will be responsible for Architecture and micro-architecture design of the ASICs, RTL design and synthesis, Logic and Timing verification using leading edge CAD tools and Semiconductor process technologies. In addition to this, you will also mentor and guide more junior engineers.
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ASIC Verification Engs/Leads
| | Company | : | Nasdaq listed fortune 500 companies.Globally know leading Semiconductor
| | Skills | : | Must be skilled in RTL Design and functional verification of large SoC's / FPGAs employing a combination of directed and formal techniques. Hands-on experience with different aspects of verification like logic equivalence, property checking, functional & code coverage metrics, assertions, timing verification desired. Should be skilled in Verilog/VHDL coding, experienced with tools such as VCS/NC-Verilog/Modelsim. Prior work experience with verification of embedded processor cores shall be a plus . Knowledge of PERL/TCL and scripting is a must . Higher level language experience with System C , System Verilog shall be a plus . Familiarity with silicon validation desired.
| | Experience | : | 4-10 yrs
| | Job Description | : | - Develop and tune the verification environment and methodology for industry's leading Graphics, Video and Media & Communications Processors.
Specific areas include 2D and 3D graphics, mpeg, video, audio, network protocols, high-speed IO interfaces and bus protocols, and memory subsystem design.
- Create test plans for both unit-level and chip-level environments
- Design and implement design verification environments
- Code testbenches using Verilog and C PLI
- Write tools in Perl and shell scripts
- Utilize advanced verification tools, formal verification, emulation, and code coverage
- Generate tests and debug the Verilog design
- Mentor and guide junior engineers
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A Technology Director - SONET / SDH / Ethernet / DWDM / OTN
| | Company | : | A Global leader in Optical, Ethernet and data networking solutions - a client of Concorde Management Consultants
| | Skills | : | „X Deep understanding of Layer 1 and Layer 2 technologies and applications
„X Excellent communication skills and strong ¡¥influential¡¦ leader
„X Strong relationships with Technology opinion leaders with Carrier organizations
„X A technology plus business mindset
„XDependable, team player with strong work ethic
„X Comfortable with working independently
„X Willingness to travel within India and overseas, frequently
„X Strong personality and ¡¥gravitas¡¦ ¡V ability to engage in healthy debates internally and externally. Desire and ability to influence others.
„X Ability to work well both with the India team and the global Ciena team
| | Experience | : | 15 - 25 Yrs
| | Job Description | : | Position requires close interaction with the CTO office, PLM and the Asia sales and marketing teams. India Technology Director is responsible for facilitating strategic product positioning, next generation feature requirements, planning and execution of the product portfolio in India. Requirements include:
„X Identifying technology/applications trends in India that Ciena can take advantage of.
„X Engaging with customers on a regular basis to understand their future needs and further Ciena¡¦s technology agenda
„X Providing expert technology support for new product introduction in strategic accounts.
„X Helping further Ciena¡¦s brand image in the technology circles, in India
„XWorking closely with CTO office representatives in other regions to address entry of carriers in those regions, who are now entering India (e.g., ATT, BT, C&W etc.)
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| | Company | : | A Global leader in Optical, Ethernet and data networking solutions - a client of Concorde Management Consultants
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Memory circuit design Engs/Leads
| | Company | : | Nasdaq listed fortune 500 companies.Globally know leading Semiconductor
| | Skills | : | Good knowledge of CMOS VLSI design (analog and digital)
In depth knowledge of CMOS circuit design principles
Memory (RAM, ROM, RF etc) architecture knowledge
Knowledge of UDSM design issues
Experience with schematic design, layout, extraction and simulation
Knowledge of cadence design tools with experience on spice simulator, parasitic extractor is must
Knowledge of CMOS process, DFM, design rules, yield etc.
Knowledge of scripting skills (Perl/TCL).
| | Experience | : | 3-10 yrs
| | Job Description | : | Work on different type of memory (RAM, ROM & Register File) architecture and circuit design
Work on circuit design methodology for UDSM technology nodes
Circuit simulations for power and timing closure
Margin analysis and circuit optimization
Characterization and compiler QA
Work closely with layout design team to integrate circuit design decision with layout constraints
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System Modeling Engineer
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Responsible for building and verifying high level models and frameworks for microprocessor cores and full fledged SoC systems, for usage by internal and external SoC design/product teams.
Excellent proficiency in C++ and OOAD, with knowledge on UNIX shell scripts, CVS, g++, gdb, Perl, gmake are pre-requisites for the job. Experience in using/applying UML and Design Patterns and working with large code-base software in C++ is desirable.
Exposure to software processes and documentation (doxygen, reports, user manuals, etc), is a definite plus.
Experience in building and verifying high level cycle accurate, functional models for microprocessor cores and full fledged SoCs and knowledge of SystemC would be an added plus.
Prior understanding of PowerPC architecture is a definite plus.
| | Experience | : | 4 - 8 Years
| | Job Description | : | Responsible for building and verifying high level models and frameworks for microprocessor cores and full fledged SoC systems, for usage by internal and external SoC design/product teams.
Excellent proficiency in C++ and OOAD, with knowledge on UNIX shell scripts, CVS, g++, gdb, Perl, gmake are pre-requisites for the job. Experience in using/applying UML and Design Patterns and working with large code-base software in C++ is desirable.
Exposure to software processes and documentation (doxygen, reports, user manuals, etc), is a definite plus.
Experience in building and verifying high level cycle accurate, functional models for microprocessor cores and full fledged SoCs and knowledge of SystemC would be an added plus.
Prior understanding of PowerPC architecture is a definite plus.
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DFT Engs/leads
| | Company | : | Nasdaq listed fortune 500 companies.
| | Skills | : | Test Encounter, Fastcan, DFT Advisor, Testkompress, Logic Test, Memory Test, Interface test, atpg, Mbist, IO bist, Memory Bist, Jtag, DFT compiler, DFT, Design for test, design for testability
| | Experience | : | 2 - 10 Year
| | Job Description | : | o Experience in Perl/Tcl scripting, DFT tools (memory bist, atpg), simulation tools (VCS, MODELSIM). Knowledge/understanding in Synthesis, STA.
o Define and Implement DFT structures, validate, support post-silicon bring-up and release to production efforts.
o DFT for microprocessor core platforms and SOCs with tasks ranging from defining the SOC test architecture to DFT implementation and verification.
o Hands-on experience with Test Encounter/Fastcan/DFT Advisor/Testkompress is a pre-requisite for the job.
o Architect SOC DFT
o DFT execution managing all the interfaces.
o Strong logic Design and verification back ground with experience in STA.
o Must possess a strong knowledge of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
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Board Design Leads/Managers
| | Company | : | A Leading Semiconductor Company
| | Skills | : | Strong knowledge of high speed digital design concepts, including SI and EMI/EMC related concepts. Strong knowledge of High speed IO technologies.
Expertise on board development cycle starting from concept to the final product delivery
Strong knowledge of Telecom and networking domain technologies including SONET/SDH, GbE, 10GbE, ATM, DS3, T1/E1, ESCON, FICON, Fiber Channel, DSL, RS232/485, etc
Hands on experience with schematic capture tools like DxDesigner and Layout tools like Allegro, PADS etc.
Strong Leadership and motivational skills
Excellent written and verbal communication skills, interpersonal skills
Ability to resolve complex issues that may require design tradeoffs
Strong problem solving and analytical skills.
| | Experience | : | 6 - 15 Yrs
| | Job Description | : | Designing and Validating reference board designs for the Consumer/Telecom/Networking market.
Experience with multilayer board design, testing and integration.
Strong knowledge of high speed digital design concepts, including SI and EMI/EMC related concepts. Strong knowledge of High speed IO technologies.
Expertise on board development cycle starting from concept to the final product delivery
Strong knowledge of Telecom and networking domain technologies including SONET/SDH, GbE, 10GbE, ATM, DS3, T1/E1, ESCON, FICON, Fiber Channel, DSL, RS232/485, etc
Hands on experience with schematic capture tools like DxDesigner and Layout tools like Allegro, PADS etc.
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Analog design
| | Skills | : | Responsible for designing, developing, modifying and evaluating electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review vendor capability to support development.
Follows standard practices and procedure in analyzing situations or data from which answers can be readily obtained. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry
| | Experience | : | 3 -12 Yrs
| | Job Description | : | Responsible for designing, developing, modifying and evaluating electronic parts, components or integrated circuitry for electronic equipment and other hardware systems. Determines design approaches and parameters. Analyzes equipment to establish operating data, conducts experimental tests and evaluates results. Selects components and equipment based on analysis of specifications and reliability. May also review vendor capability to support development.
Follows standard practices and procedure in analyzing situations or data from which answers can be readily obtained. Requires a BS degree or equivalent experience in the design of equipment, components or circuitry
Major Duties :-
Design of Mixed Signal Integrated Circuits. The work involves design of various analog blocks like Operational Amplifiers, Comparators, Oscillator, Analog to Digital Converter, etc.
Closing Statement:-
The knowledge of various tools used in analog design like Spice/Spectre, Cadence design environment will be required.
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Standard Cell Circuit Design - Engs/Leads - Top Semiconductor companies
| | Company | : | Nasdaq listed fortune 500 companies.
| | Skills | : | o Knowledge of basic electronics and MOS circuit design fundamentals is must
o Knowledge of cadence tools and simulations with experience on eldo/hspice is must.
o Knowledge of scripting skills.
o Standard cell layout domain know-how is required.
o Knowledge of cadence skill language is required
| | Experience | : | 2 - 8 yrs
| | Job Description | : | • Technology study for new technology nodes
• Sizing analysis/study based on model performance
• Circuit design for standard cell libraries.
• Methodology definition and circuit design for differentiated performance libraries
• Working with layout development to integrate circuit design decision with layout constraints
• 2 to 4 years of experience for Engineer positions
• 4-7 years plus for Lead Positions
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Memory circuit design Managers - Top Semiconductor Companies
| | Company | : | Nasdaq listed fortune 500 companies.
| | Skills | : | o Good knowledge of CMOS VLSI design (analog and digital)
o In depth knowledge of CMOS circuit design principles
o Memory (RAM, ROM, RF etc) architecture knowledge
o Knowledge of UDSM design issues
o Experience with schematic design, layout, extraction and simulation
o Knowledge of cadence design tools with experience on spice simulator, parasitic extractor is must
o Knowledge of CMOS process, DFM, design rules, yield etc.
o Knowledge of scripting skills (Perl/TCL).
| | Experience | : | 7-15 yrs
| | Job Description | : | 1. Work on different type of memory (RAM, ROM & Register File) architecture and circuit design
2. Work on circuit design methodology for UDSM technology nodes
3. Circuit simulations for power and timing closure
4. Margin analysis and circuit optimization
5. Characterization and compiler QA
6. Work closely with layout design team to integrate circuit design decision with layout constraints
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SRAM Quality Engineer/Lead - Top Semiconductor Companies
| | Company | : | Nasdaq listed fortune 500 companies.
| | Skills | : | • Candidate must possess at least a Bachelor of Engineering/Technology or Master of Engineering/Technology in Engineering (Electronics/Telecommunication),
• * Good Knowledge of different types Memories.
• *Good Knowledge of Perl, Tcl Scripting Languages.
• *Familiar with Cadence Tools (SOC Encounter, icfb)
• * Full-Time positions
| | Experience | : | 4-8yrs
| | Job Description | : | • Support of Internal and external Memory Compilers.
• Validation of Front End and Back End Views.
• Automation of Validation setups.
• Development of LEF, celtic, Vstorm views
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